`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:06:53 03/26/2014
// Design Name:   Omega_3x8
// Module Name:   C:/Users/rpobrien/Documents/School/cis6930-network-security/SBoxCipher/Omega_3x8_tb.v
// Project Name:  SBoxCipher
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Omega_3x8
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Omega_3x8_tb;

	// Inputs
	reg [127:0] data_in;
	wire [127:0] data_out;
	reg [23:0] sel;

	// Instantiate the Unit Under Test (UUT)
	Omega_3x8 uut (
		.data_in(data_in), 
		.data_out(data_out), 
		.sel(sel)
	);

	initial begin
		// Initialize Inputs
		data_in = 0;
		sel = "FAC";

		// Wait 100 ns for global reset to finish
		#100;
		data_in = "ABCDEFGHIJKLMNOP";
		#10;
		$display("IN:\t%s", data_in);
		$display("OUT:\t%s", data_out);
		#100;
		data_in = "KLMNOPQRSTUVWXYZ";
		#10;
		$display("IN:\t%s", data_in);
		$display("OUT:\t%s", data_out);
		#100;
		data_in = "HELLO BIG KITTY!";
		#10;
		$display("IN:\t%s", data_in);
		$display("OUT:\t%s", data_out);
		
		//outfile = $fopen("Inputs/test_out.txt", "w");
		//$fwrite(outfile, "%c", data_out[7:0]);
		//$fclose(outfile);		
		
		/*
		
		infile = $fopen("Inputs/test.txt", "r");
		outfile = $fopen("Inputs/test_out.txt", "w");
		for (i = 0; i < 16; i = i + 1)
		begin
			block[i] = $fgetc(infile);
			if ($feof(infile))
				i = 16;
		end
		
		
		while (!$feof(infile))
		begin
			c = $fgetc(infile);
			$display("%c", c);
		end
		
		
		$fclose(infile);
		$fclose(outfile);
		*/
        
		// Add stimulus here

	end
      
endmodule

